| Job Description : |
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Austin, TX, USA; San Diego, CA, USA.
Minimum qualifications:
Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
3 years of experience verifying digital logic at Register-Transfer level (RTL) using SystemVerilog for FPGAs and/or ASICs.
Experience working with and developing verification components/environments in verification methodology.
Experience verifying digital systems using IP components/interconnects (i.e. microprocessor cores, hierarchical memory subsystems).
Preferred qualifications:
Master’s or PhD in Electrical Engineering or Computer Science.
Experience with cryptographic IP, secure debug, and secure boot verification.
Experience with side-channel and fault injection countermeasures verification.
Experience writing C tests.
Experience with advanced verification techniques.
About the job
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
As an ASIC Design Verification Engineer, you will be part of a Research and Development team and responsible for building verification components, constrained-random testing, system testing, and verification closure.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, and verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification gaps and to show progress towards tape-out.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. |
